diff --git a/bsp/README.md b/bsp/README.md index 233ecea93c0..ac33dea0a63 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -317,23 +317,23 @@ This document is based on the RT-Thread mainline repository and categorizes the #### 🟡 N32 -| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH | +| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH | SDRAM | LCDC | |----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----| -| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | -| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | -| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | -| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - | - | - | +| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | +| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | +| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | #### 🟡 NRF5x diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lcd.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lcd.c new file mode 100644 index 00000000000..25008834aa8 --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lcd.c @@ -0,0 +1,389 @@ +/* + * Copyright (c) 2006-2025 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-07-08 ox-horse first version + */ + +#include + +#ifdef BSP_USING_LCD +#include +#include +#include "n32h7xx_lcdc.h" + +#define DRV_DEBUG +#define LOG_TAG "drv.lcd" +#include + +#define LCD_BUF_SIZE (BSP_LCD_WIDTH_PIXEL * BSP_LCD_HEIGHT_PIXEL * BSP_BITS_PER_PIXEL / 8U) +#define LCD_DEVICE(dev) (struct drv_lcd_device *)(dev) + +struct drv_lcd_device +{ + struct rt_device parent; + + struct rt_device_graphic_info lcd_info; + + struct rt_semaphore lcd_lock; +}; + +struct drv_lcd_device _lcd; + +static rt_err_t drv_lcd_init(struct rt_device *device) +{ + struct drv_lcd_device *lcd = LCD_DEVICE(device); + /* nothing, right now */ + (void)lcd; + return RT_EOK; +} + +static rt_err_t drv_lcd_control(struct rt_device *device, int cmd, void *args) +{ + struct drv_lcd_device *lcd = LCD_DEVICE(device); + + switch (cmd) + { + case RTGRAPHIC_CTRL_RECT_UPDATE: + { + rt_sem_take(&_lcd.lcd_lock, RT_TICK_PER_SECOND / 20); + LCDC_ReloadConfig(LCDC_VBRELOAD); + } + break; + + case RTGRAPHIC_CTRL_GET_INFO: + { + struct rt_device_graphic_info *info = (struct rt_device_graphic_info *)args; + + RT_ASSERT(info != RT_NULL); + info->pixel_format = lcd->lcd_info.pixel_format; + info->bits_per_pixel = lcd->lcd_info.bits_per_pixel; + info->width = lcd->lcd_info.width; + info->height = lcd->lcd_info.height; + info->framebuffer = lcd->lcd_info.framebuffer; + } + break; + + default: + return -RT_EINVAL; + } + + return RT_EOK; +} + +/** + * LCDC event interrupt handler. Handles: + * - Line interrupt (LI): fired at configured scan line position + * - FIFO underrun interrupt (FU): FIFO empty during active data phase + * - Register reload interrupt (RR): fired after vertical blanking reload, used for frame sync + */ +void LCD_EV_IRQHandler(void) +{ + rt_interrupt_enter(); + + /* Line interrupt: triggered at configured scan line position */ + if (LCDC_GetFlagStatus(LCDC_FLAG_L)) + { + LCDC_ClearFlag(LCDC_FLAG_L); + } + + /* FIFO underrun: FIFO empty during active data phase */ + if (LCDC_GetFlagStatus(LCDC_FLAG_FU)) + { + LCDC_ClearFlag(LCDC_FLAG_FU); + LOG_E("LCDC FIFO underrun"); + } + + /* Register reload complete: release semaphore for frame sync */ + if (LCDC_GetFlagStatus(LCDC_FLAG_RR)) + { + LCDC_ClearFlag(LCDC_FLAG_RR); + rt_sem_release(&_lcd.lcd_lock); + } + + rt_interrupt_leave(); +} + +/** + * LCDC error interrupt handler. Handles: + * - BUS error interrupt (BE): AHB bus error during transfer + */ +void LCD_ER_IRQHandler(void) +{ + rt_interrupt_enter(); + + if (LCDC_GetFlagStatus(LCDC_FLAG_BE)) + { + LCDC_ClearFlag(LCDC_FLAG_BE); + LOG_E("LCDC AHB bus error"); + } + + rt_interrupt_leave(); +} + +/** + * Configure LCDC power domain, peripheral clocks and pixel clock. + * This function provides a default configuration for N32H7xx HMI boards. + * Override this function at the board level if different clock settings are needed. + */ +rt_weak void n32_lcd_clock_config(void) +{ + /* Enable LCDC power domain */ + PWR_MoudlePowerEnable(GRAPHIC_LCDC_PWRCTRL, ENABLE); + + /* Enable LCDC AXI peripheral clocks (LCDC core, low-power, APB, APB low-power) */ + RCC_EnableAXIPeriphClk2(RCC_AXI_PERIPHEN_M7_LCDC | RCC_AXI_PERIPHEN_M7_LCDCLP | + RCC_AXI_PERIPHEN_M7_LCDCAPB | RCC_AXI_PERIPHEN_M7_LCDCAPBLP, + ENABLE); + + /* Configure pixel clock source: AXI divided by 8 (600MHz / 8 = 75MHz) */ + RCC_ConfigLCDCPixelClk(RCC_LCDCPIXELCLK_SRC_AXIDIV, RCC_LCDCPIXELCLK_AXIDIV8); +} + +static rt_err_t n32_lcd_init(struct drv_lcd_device *lcd) +{ + LCDC_InitType LCDC_InitStruct; + LCDC_Layer_InitType LCDC_Layer_InitStruct; + + /* Configure LCDC power and clocks */ + n32_lcd_clock_config(); + + /* Initialize structs with default values */ + LCDC_StructInit(&LCDC_InitStruct); + LCDC_LayerStructInit(&LCDC_Layer_InitStruct); + + /* Polarity configuration */ + LCDC_InitStruct.LCDC_HSPolarity = LCDC_HSPOLARITY_LOW; + LCDC_InitStruct.LCDC_VSPolarity = LCDC_VSPOLARITY_LOW; + LCDC_InitStruct.LCDC_DEPolarity = LCDC_DEPOLARITY_LOW; + LCDC_InitStruct.LCDC_PCPolarity = LCDC_PCPOLARITY_IPC; + + /* Timing configuration */ + /* Horizontal synchronization width = HSW - 1 */ + LCDC_InitStruct.LCDC_HorizontalSync = BSP_LCD_HSYNC_WIDTH_PIXEL - 1; + /* Vertical synchronization height = VSW - 1 */ + LCDC_InitStruct.LCDC_VerticalSync = BSP_LCD_VSYNC_HEIGHT_PIXEL - 1; + /* Accumulated horizontal back porch = HSW + HBP - 1 */ + LCDC_InitStruct.LCDC_AccumulatedHBP = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL - 1; + /* Accumulated vertical back porch = VSW + VBP - 1 */ + LCDC_InitStruct.LCDC_AccumulatedVBP = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL - 1; + /* Accumulated active width = HSW + HBP + Active Width - 1 */ + LCDC_InitStruct.LCDC_AccumulatedActiveW = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL + lcd->lcd_info.width - 1; + /* Accumulated active height = VSW + VBP + Active Height - 1 */ + LCDC_InitStruct.LCDC_AccumulatedActiveH = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL + lcd->lcd_info.height - 1; + /* Total height = VSW + VBP + Active Height + VFP - 1 */ + LCDC_InitStruct.LCDC_TotalHeight = LCDC_InitStruct.LCDC_AccumulatedActiveH + BSP_LCD_VFP_PIXEL; + /* Total width = HSW + HBP + Active Width + HFP - 1 */ + LCDC_InitStruct.LCDC_TotalWidth = LCDC_InitStruct.LCDC_AccumulatedActiveW + BSP_LCD_HFP_PIXEL; + + /* Configure R,G,B component values for LCD background color: black */ + LCDC_InitStruct.LCDC_BackgroundRedValue = 0; + LCDC_InitStruct.LCDC_BackgroundGreenValue = 0; + LCDC_InitStruct.LCDC_BackgroundBlueValue = 0; + + /* Initialize LCDC global registers */ + LCDC_Init(&LCDC_InitStruct); + + /* Layer 1 Configuration */ + + /* Windowing configuration */ + LCDC_Layer_InitStruct.LCDC_HorizontalStart = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL; + LCDC_Layer_InitStruct.LCDC_HorizontalStop = BSP_LCD_HSYNC_WIDTH_PIXEL + BSP_LCD_HBP_PIXEL + lcd->lcd_info.width - 1; + LCDC_Layer_InitStruct.LCDC_VerticalStart = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL; + LCDC_Layer_InitStruct.LCDC_VerticalStop = BSP_LCD_VSYNC_HEIGHT_PIXEL + BSP_LCD_VBP_PIXEL + lcd->lcd_info.height - 1; + + /* Pixel Format configuration */ + if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB565) + { + LCDC_Layer_InitStruct.LCDC_PixelFormat = LCDC_PIXEL_FORMAT_RGB565; + } + else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_ARGB888) + { + LCDC_Layer_InitStruct.LCDC_PixelFormat = LCDC_PIXEL_FORMAT_ARGB8888; + } + else if (lcd->lcd_info.pixel_format == RTGRAPHIC_PIXEL_FORMAT_RGB888) + { + LCDC_Layer_InitStruct.LCDC_PixelFormat = LCDC_PIXEL_FORMAT_RGB888; + } + else + { + LOG_E("unsupported pixel format"); + return -RT_ERROR; + } + + /* Start Address configuration: point LCDC directly at framebuffer (zero-copy) */ + LCDC_Layer_InitStruct.LCDC_CFBStartAdress = (uint32_t)lcd->lcd_info.framebuffer; + + /* Alpha constant (255 = totally opaque) */ + LCDC_Layer_InitStruct.LCDC_ConstantAlpha = 255; + + /* Default Color configuration */ + LCDC_Layer_InitStruct.LCDC_DefaultAlpha = 0; + LCDC_Layer_InitStruct.LCDC_DefaultColorRed = 0; + LCDC_Layer_InitStruct.LCDC_DefaultColorGreen = 0; + LCDC_Layer_InitStruct.LCDC_DefaultColorBlue = 0xFF; + + /* Configure blending factors: Constant Alpha blending */ + LCDC_Layer_InitStruct.LCDC_BlendingFactor1 = LCDC_BLENDING_FACTOR1_CA; + LCDC_Layer_InitStruct.LCDC_BlendingFactor2 = LCDC_BLENDING_FACTOR2_CA; + + /* Configure the line length, pitch and number of lines */ + LCDC_Layer_InitStruct.LCDC_CFBLineLength = (lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8)) + 7; + LCDC_Layer_InitStruct.LCDC_CFBPitch = lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8); + LCDC_Layer_InitStruct.LCDC_CFBLineNumber = lcd->lcd_info.height; + + /* Initialize LCDC Layer 1 */ + LCDC_LayerInit(LCDC_Layer1, &LCDC_Layer_InitStruct); + + /* Reload layer config immediately */ + LCDC_LayerReloadConfig(LCDC_Layer1, LCDC_LAYER_IMRELOAD); + + /* Enable Layer 1 */ + LCDC_LayerEnable(LCDC_Layer1, ENABLE); + + /* Reload layer config again after enable */ + LCDC_LayerReloadConfig(LCDC_Layer1, LCDC_LAYER_IMRELOAD); + + /* Enable LCDC */ + LCDC_Enable(ENABLE); + + /* Configure line interrupt to trigger at last active line (reserved for TE sync) */ + LCDC_LINTPConfig(LCDC_InitStruct.LCDC_AccumulatedActiveH); + + /* Enable LCDC event interrupts: RR (frame sync), LI (line interrupt), FU (FIFO underrun) */ + LCDC_ConfigInt(LCDC_INT_RRIEN | LCDC_INT_LIEN | LCDC_INT_FUIEN, ENABLE); + + /* Enable LCDC error interrupts: BE (AHB bus error) */ + LCDC_ConfigInt(LCDC_INT_BEIEN, ENABLE); + + /* Configure NVIC for LCDC event and error interrupts */ + NVIC_SetPriority(LCD_EV_IRQn, 1); + NVIC_EnableIRQ(LCD_EV_IRQn); + NVIC_SetPriority(LCD_ER_IRQn, 1); + NVIC_EnableIRQ(LCD_ER_IRQn); + + LOG_D("LCDC init success"); + return RT_EOK; +} + +#if defined(BSP_LCD_BACKLIGHT_USING_PWM) +void turn_on_lcd_backlight(void) +{ + struct rt_device_pwm *pwm_dev; + + /* turn on the LCD backlight */ + pwm_dev = (struct rt_device_pwm *)rt_device_find(BSP_LCD_PWM_DEV_NAME); + /* pwm frequency: 100K = 10000ns */ + rt_pwm_set(pwm_dev, BSP_LCD_PWM_DEV_CHANNEL, 10000, 10000); + rt_pwm_enable(pwm_dev, BSP_LCD_PWM_DEV_CHANNEL); +} +#elif defined(BSP_LCD_BACKLIGHT_USING_GPIO) +void turn_on_lcd_backlight(void) +{ + rt_pin_mode(BSP_LCD_BACKLIGHT_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(BSP_LCD_DISPLAY_PIN, PIN_MODE_OUTPUT); + + rt_pin_write(BSP_LCD_DISPLAY_PIN, PIN_HIGH); + rt_pin_write(BSP_LCD_BACKLIGHT_PIN, PIN_HIGH); +} +#else +void turn_on_lcd_backlight(void) +{ +} +#endif + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops lcd_ops = { + drv_lcd_init, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + drv_lcd_control +}; +#endif + +int drv_lcd_hw_init(void) +{ + rt_err_t result = RT_EOK; + struct rt_device *device = &_lcd.parent; + + /* memset _lcd to zero */ + memset(&_lcd, 0x00, sizeof(_lcd)); + + /* init lcd_lock semaphore */ + result = rt_sem_init(&_lcd.lcd_lock, "lcd_lock", 0, RT_IPC_FLAG_FIFO); + if (result != RT_EOK) + { + LOG_E("init semaphore failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + /* config LCD dev info */ + _lcd.lcd_info.height = BSP_LCD_HEIGHT_PIXEL; + _lcd.lcd_info.width = BSP_LCD_WIDTH_PIXEL; + _lcd.lcd_info.bits_per_pixel = BSP_BITS_PER_PIXEL; + +#if defined(BSP_LCD_PIXEL_FORMAT_RGB565) + _lcd.lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; +#elif defined(BSP_LCD_PIXEL_FORMAT_ARGB8888) + _lcd.lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888; +#elif defined(BSP_LCD_PIXEL_FORMAT_RGB888) + _lcd.lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888; +#endif + + /* malloc single framebuffer (zero-copy, LCDC points directly to this buffer) */ + _lcd.lcd_info.framebuffer = rt_malloc_align(LCD_BUF_SIZE, 64); + if (_lcd.lcd_info.framebuffer == RT_NULL) + { + LOG_E("init frame buffer failed!\n"); + result = -RT_ENOMEM; + goto __exit; + } + + /* memset buff to 0xFF (white) */ + memset(_lcd.lcd_info.framebuffer, 0xFF, LCD_BUF_SIZE); + + device->type = RT_Device_Class_Graphic; +#ifdef RT_USING_DEVICE_OPS + device->ops = &lcd_ops; +#else + device->init = drv_lcd_init; + device->control = drv_lcd_control; +#endif + + /* register lcd device */ + rt_device_register(device, "lcd", RT_DEVICE_FLAG_RDWR); + + /* init N32 LCDC */ + if (n32_lcd_init(&_lcd) != RT_EOK) + { + LOG_E("lcd hardware init failed"); + result = -RT_ERROR; + goto __exit; + } + else + { + turn_on_lcd_backlight(); + } + +__exit: + if (result != RT_EOK) + { + rt_sem_detach(&_lcd.lcd_lock); + + if (_lcd.lcd_info.framebuffer) + { + rt_free_align(_lcd.lcd_info.framebuffer); + } + } + return result; +} +INIT_DEVICE_EXPORT(drv_lcd_hw_init); + + +#endif /* BSP_USING_LCD */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c new file mode 100644 index 00000000000..54edd4371bd --- /dev/null +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdram.c @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-21 ox-horse first version for N32, based on N32 SDK bsp_sdram.c + */ + +#include +#include + +#ifdef BSP_USING_SDRAM +#include +#include +#include + +#define DRV_DEBUG +#define LOG_TAG "drv.sdram" +#include + +#ifdef RT_USING_MEMHEAP_AS_HEAP +static struct rt_memheap system_heap; +#endif + +static SDRAM_DeviceType sdram_device; + +/*---------------------------------------------------------------------------- + * Macro translation: standard sdram_port.h -> N32 HAL + *---------------------------------------------------------------------------*/ + +/* Row bits + Column bits -> N32 address configuration */ +#if SDRAM_ROW_BITS == 11 +#if SDRAM_COLUMN_BITS == 8 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL256 +#elif SDRAM_COLUMN_BITS == 9 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL512 +#elif SDRAM_COLUMN_BITS == 10 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL1024 +#elif SDRAM_COLUMN_BITS == 11 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW2048_COL2048 +#endif +#elif SDRAM_ROW_BITS == 12 +#if SDRAM_COLUMN_BITS == 8 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL256 +#elif SDRAM_COLUMN_BITS == 9 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL512 +#elif SDRAM_COLUMN_BITS == 10 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL1024 +#elif SDRAM_COLUMN_BITS == 11 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW4096_COL2048 +#endif +#elif SDRAM_ROW_BITS == 13 +#if SDRAM_COLUMN_BITS == 8 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL256 +#elif SDRAM_COLUMN_BITS == 9 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL512 +#elif SDRAM_COLUMN_BITS == 10 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL1024 +#elif SDRAM_COLUMN_BITS == 11 +#define SDRAM_ADDR_CFG SDRAM_BANK4_ROW8192_COL2048 +#endif +#endif + +/* Data width -> N32 bus width */ +#if SDRAM_DATA_WIDTH == 8 +#define SDRAM_HAL_BUS_WIDTH SDRAM_DEVICE_BUSWID_8BITS +#define SDRAM_HAL_BURSTLEN SDRAM_DEVICE_BURSTLEN_8 +#define SDRAM_LOADMODE_BURSTLEN 3 +#elif SDRAM_DATA_WIDTH == 16 +#define SDRAM_HAL_BUS_WIDTH SDRAM_DEVICE_BUSWID_16BITS +#define SDRAM_HAL_BURSTLEN SDRAM_DEVICE_BURSTLEN_4 +#define SDRAM_LOADMODE_BURSTLEN 2 +#elif SDRAM_DATA_WIDTH == 32 +#define SDRAM_HAL_BUS_WIDTH SDRAM_DEVICE_BUSWID_32BITS +#define SDRAM_HAL_BURSTLEN SDRAM_DEVICE_BURSTLEN_2 +#define SDRAM_LOADMODE_BURSTLEN 1 +#endif + +/* CAS latency -> N32 CAS */ +#ifdef BSP_SDRAM_CAS_LATENCY_1 +#define SDRAM_HAL_CAS_LATENCY SDRAM_DEVICE_CASLTCY_1 +#define SDRAM_LOADMODE_CASLATENCY 1 +#endif /* BSP_SDRAM_CAS_LATENCY_1 */ +#ifdef BSP_SDRAM_CAS_LATENCY_2 +#define SDRAM_HAL_CAS_LATENCY SDRAM_DEVICE_CASLTCY_2 +#define SDRAM_LOADMODE_CASLATENCY 2 +#endif /* BSP_SDRAM_CAS_LATENCY_2 */ +#ifdef BSP_SDRAM_CAS_LATENCY_3 +#define SDRAM_HAL_CAS_LATENCY SDRAM_DEVICE_CASLTCY_3 +#define SDRAM_LOADMODE_CASLATENCY 3 +#endif /* BSP_SDRAM_CAS_LATENCY_3 */ + +/* Target bank -> device select */ +#ifdef BSP_SDRAM_BANK1 +#define SDRAM_CS_SELECT SDRAM_CS_SDRAM1_ONLY +#endif +#ifdef BSP_SDRAM_BANK2 +#define SDRAM_CS_SELECT SDRAM_CS_SDRAM2_ONLY +#endif + + +#ifndef SDRAM_RP_DELAY +#define SDRAM_RP_DELAY (RPDELAY) +#endif +#ifndef SDRAM_REFRESH_CYCLE +#define SDRAM_REFRESH_CYCLE (ROWCYCLEDELAY) +#endif +#ifndef SDRAM_ADDRESS_MASK +#define SDRAM_ADDRESS_MASK ((uint32_t)(0xFFFFFFFF - ((BSP_SDRAM_SIZE * 1024U * 1024U) - 1))) +#endif + +/*---------------------------------------------------------------------------- + * SDRAM Load Mode Register type (from N32 SDK bsp_sdram.h) + * Represents the value sent to the SDRAM chip via LOADMODE command. + *---------------------------------------------------------------------------*/ +typedef union +{ + uint32_t cmd; + struct + { + uint32_t BurstLen : 3; /* M2:0 Burst Length */ + uint32_t BurstType : 1; /* M3 Burst Type */ + uint32_t CASLatency : 3; /* M6:4 CAS Latency */ + uint32_t OpMode : 2; /* M8:7 Operating Mode */ + uint32_t WBMode : 1; /* M9 Write Burst Mode */ + uint32_t Reserved : 22; + } Bits; +} SDRAM_LoadModeRegisterType; + +/* Mode register field values (from N32 SDK bsp_sdram.h) */ +#define LOADMODE_BURSTLEN_1 0 +#define LOADMODE_BURSTLEN_2 1 +#define LOADMODE_BURSTLEN_4 2 +#define LOADMODE_BURSTLEN_8 3 +#define LOADMODE_BURSTTYPE_SEQUENTIAL 0 +#define LOADMODE_BURSTTYPE_INTERLEAVED 1 +#define LOADMODE_CASLATENCY_2 2 +#define LOADMODE_CASLATENCY_3 3 +#define LOADMODE_OPMODE_STANDARD 0 +#define LOADMODE_WBMODE_BURST 0 +#define LOADMODE_WBMODE_SINGLE 1 + +/*---------------------------------------------------------------------------- + * SDRAM RCC Clock Configuration (rt_weak, override in board.c if needed) + *---------------------------------------------------------------------------*/ +rt_weak void rt_hw_sdram_clock_init(void) +{ + /* Configure SDRAM delay chain (board-specific, default 0.2ns step) */ + RCC_ConfigSDRAMDelay(RCC_SDRAM_DELAY_0_2NS); + RCC_EnableSDRAMDelayChain(ENABLE); +} + +/*---------------------------------------------------------------------------- + * SDRAM Initialization Sequence + * Based on N32 SDK SDRAM_DeviceInit() + SDRAM_OperationInit() pattern. + *---------------------------------------------------------------------------*/ +static void SDRAM_Initialization_Sequence(SDRAM_DeviceType device) +{ + SDRAM_LoadModeRegisterType load_mode; + __IO uint32_t delay; + int i; + + /*--- Configure device: address, refresh, timing, bus width, etc. ---*/ + + /* Step 1: Set device base address and address mask */ + SDRAM_SetDeviceAddress(device, SDRAM_BANK_ADDR, SDRAM_ADDRESS_MASK); + + /* Step 2: Set refresh interval */ + SDRAM_RefreshIntervalInit(SDRAM_REFRESH_COUNT); + + /* Step 3: Configure timing parameters + * Mapping: STM32-style macro -> N32 SDRAM_TimingType register field + * SELFREFRESHTIME -> RowActiveTime (tRAS) + * ROWCYCLEDELAY -> RowCycleTime (tRC) + * SDRAM_RP_DELAY -> RowActToRowActDelay (tRRD) + * RPDELAY -> PrechargeTime (tRP) + * WRITERECOVERYTIME -> WriteRecoveryTime (tWR) + * SDRAM_REFRESH_CYCLE -> RefreshCycleTime (tRFC) + * RCDDELAY -> RAstoCASDelay (tRCD) + */ + SDRAM_TimingType SDRAM_Timing; + SDRAM_Timing.RowActiveTime = SELFREFRESHTIME; + SDRAM_Timing.RowCycleTime = ROWCYCLEDELAY; + SDRAM_Timing.RowActToRowActDelay = SDRAM_RP_DELAY; + SDRAM_Timing.PrechargeTime = RPDELAY; + SDRAM_Timing.WriteRecoveryTime = WRITERECOVERYTIME; + SDRAM_Timing.RefreshCycleTime = SDRAM_REFRESH_CYCLE; + SDRAM_Timing.RAStoCASDelay = RCDDELAY; + SDRAM_TimingInit(&SDRAM_Timing); + + /* Step 4: Configure device parameters (same as SDRAM_ConfigurationInit in SDK) */ + SDRAM_EnableDevice(device, ENABLE); + SDRAM_EnableRefreshCMD(device, ENABLE); + SDRAM_EnableAutoPrecharge(device, DISABLE); + SDRAM_EnablePrefetchRead(device, DISABLE); + SDRAM_EnableSOM(device, ENABLE); + SDRAM_EnableBankInterleave(device, DISABLE); + SDRAM_ConfigBusWidth(device, SDRAM_HAL_BUS_WIDTH); + SDRAM_ConfigBurstLength(device, SDRAM_HAL_BURSTLEN); + SDRAM_ConfigCASLatency(device, SDRAM_HAL_CAS_LATENCY); + SDRAM_ConfigAddress(device, SDRAM_ADDR_CFG); + + /*--- Send command sequence: Precharge -> Auto-Refresh -> Load Mode ---*/ + + /* Step 5: Precharge all banks + * Per SDK pattern: set clock enable + opcode + chip select + bank + address, + * then trigger by dummy-read of SDRAM->OR register. */ + SDRAM_EnableClock(ENABLE); + SDRAM_SetOperationCode(SDRAM_OPCODE_PRECHRG); + SDRAM_SetDeviceSelect(SDRAM_CS_SELECT); + SDRAM_SetBank(SDRAM_BANKADD_1); + SDRAM_SetAddress(0); + (void)(SDRAM->OR); /* dummy access triggers the operation */ + + /* Step 6: Auto refresh (2 cycles, per SDK convention) */ + for (i = 0; i < 2; i++) + { + SDRAM_EnableClock(ENABLE); + SDRAM_SetOperationCode(SDRAM_OPCODE_REFRESH); + SDRAM_SetDeviceSelect(SDRAM_CS_SELECT); + SDRAM_SetBank(SDRAM_BANKADD_1); + SDRAM_SetAddress(0); + (void)(SDRAM->OR); + } + + /* Step 7: Load mode register */ + load_mode.cmd = 0; + load_mode.Bits.BurstLen = SDRAM_LOADMODE_BURSTLEN; + load_mode.Bits.BurstType = LOADMODE_BURSTTYPE_SEQUENTIAL; + load_mode.Bits.CASLatency = SDRAM_LOADMODE_CASLATENCY; + load_mode.Bits.OpMode = LOADMODE_OPMODE_STANDARD; + load_mode.Bits.WBMode = LOADMODE_WBMODE_BURST; + + SDRAM_EnableClock(ENABLE); + SDRAM_SetOperationCode(SDRAM_OPCODE_LOADMODE); + SDRAM_SetDeviceSelect(SDRAM_CS_SELECT); + SDRAM_SetBank(SDRAM_BANKADD_1); + SDRAM_SetAddress(load_mode.cmd); + (void)(SDRAM->OR); + + /* Wait at least 300us for SDRAM stabilization (per SDK) */ + for (delay = 0; delay < 0xFFFF; delay++) + ; +} +int sdram_test(void); +/*---------------------------------------------------------------------------- + * SDRAM Init (called via INIT_BOARD_EXPORT) + *---------------------------------------------------------------------------*/ +static int SDRAM_Init(void) +{ + int result = RT_EOK; + +#ifdef BSP_SDRAM_BANK1 + sdram_device = SDRAM_DEVICE_1; +#endif +#ifdef BSP_SDRAM_BANK2 + sdram_device = SDRAM_DEVICE_2; +#endif + + /* Reset SDRAM peripheral to default state */ + SDRAM_DeInit(); + + /* Initialize SDRAM clock (board-specific, weak function) */ + rt_hw_sdram_clock_init(); + + /* Configure and initialize the SDRAM device */ + SDRAM_Initialization_Sequence(sdram_device); + + LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", + SDRAM_BANK_ADDR, (BSP_SDRAM_SIZE * 1024U * 1024U), SDRAM_DATA_WIDTH); + +#ifdef RT_USING_MEMHEAP_AS_HEAP + /* Register SDRAM as system heap */ + rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, (BSP_SDRAM_SIZE * 1024U * 1024U)); + LOG_D("memheap registered: name=%s, start=0x%X, size=%d", + ((struct rt_object *)&system_heap)->name, + system_heap.start_addr, system_heap.pool_size); +#endif + + + return result; +} +INIT_BOARD_EXPORT(SDRAM_Init); + +/*---------------------------------------------------------------------------- + * SDRAM Test Command (Finsh shell, enabled by DRV_DEBUG) + *---------------------------------------------------------------------------*/ +#ifdef DRV_DEBUG +//#ifdef FINSH_USING_MSH +int sdram_test(void) +{ + int i = 0; + uint32_t start_time = 0, time_cast = 0; +#if SDRAM_DATA_WIDTH == 8 + char data_width = 1; + uint8_t data = 0; +#elif SDRAM_DATA_WIDTH == 16 + char data_width = 2; + uint16_t data = 0; +#else + char data_width = 4; + uint32_t data = 0; +#endif + + /* Write data */ + LOG_D("Writing %ld bytes data, waiting...", (BSP_SDRAM_SIZE * 1024U * 1024U)); + start_time = rt_tick_get(); + for (i = 0; i < (BSP_SDRAM_SIZE * 1024U * 1024U) / data_width; i++) + { +#if SDRAM_DATA_WIDTH == 8 + *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)(i % 100); +#elif SDRAM_DATA_WIDTH == 16 + *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000); +#else + *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)(i % 1000); +#endif + } + time_cast = rt_tick_get() - start_time; + LOG_D("Write done, time: %d.%03dS.", + time_cast / RT_TICK_PER_SECOND, + time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND + 999) / 1000)); + + /* Read and verify */ + LOG_D("Reading and verifying data, waiting..."); + for (i = 0; i < (BSP_SDRAM_SIZE * 1024U * 1024U) / data_width; i++) + { +#if SDRAM_DATA_WIDTH == 8 + data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width); + if (data != (uint8_t)(i % 100)) + { + LOG_E("SDRAM test failed at offset 0x%X!", i * data_width); + break; + } +#elif SDRAM_DATA_WIDTH == 16 + data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width); + if (data != (uint16_t)(i % 1000)) + { + LOG_E("SDRAM test failed at offset 0x%X!", i * data_width); + break; + } +#else + data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width); + if (data != i % 1000) + { + LOG_E("SDRAM test failed at offset 0x%X!", i * data_width); + break; + } +#endif + } + + if (i >= (BSP_SDRAM_SIZE * 1024U * 1024U) / data_width) + { + LOG_D("SDRAM test success!"); + } + + return RT_EOK; +} +MSH_CMD_EXPORT(sdram_test, sdram read / write test) +//#endif /* FINSH_USING_MSH */ +#endif /* DRV_DEBUG */ + +#endif /* BSP_USING_SDRAM */ diff --git a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c index f8bc39a083a..07430d8745c 100644 --- a/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c +++ b/bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c @@ -88,8 +88,8 @@ static int int_pow(int x, int y) if (y < 0) return -1; - int result = 1; - int base = x; + int result = 1; + int base = x; int exponent = y; /* Fast exponentiation algorithm (binary exponentiation) */ @@ -124,7 +124,7 @@ void n32_tim_ahbx_div_get(TIM_Module *timer, rt_uint32_t *div) *div = 1; #if defined(SOC_SERIES_N32H7xx) - rt_uint8_t tim_div, i; + rt_uint8_t tim_div, i; const rt_uint8_t div_group[] = { 0x00U, 0x04U, 0x05U, 0x06U, 0x07U }; if ((timer == BTIM1) || (timer == BTIM2) || (timer == BTIM3) || (timer == BTIM4)) @@ -342,9 +342,9 @@ enum struct n32_clock_timer { rt_clock_timer_t time_device; - TIM_Module *timer; - IRQn_Type tim_irqn; - char *name; + TIM_Module *timer; + IRQn_Type tim_irqn; + char *name; }; static struct n32_clock_timer n32_clock_timer_obj[] = { @@ -423,11 +423,11 @@ static struct n32_clock_timer n32_clock_timer_obj[] = { static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) { - uint32_t prescaler_value = 0; - rt_uint32_t tim_div; + uint32_t prescaler_value = 0; + rt_uint32_t tim_div; struct n32_clock_timer *tim_device = RT_NULL; - RCC_ClocksTypeDef RCC_Clocks; - TIM_TimeBaseInitType TIM_TimeBaseStructure; + RCC_ClocksTypeDef RCC_Clocks; + TIM_TimeBaseInitType TIM_TimeBaseStructure; RT_ASSERT(timer != RT_NULL); if (state) @@ -467,9 +467,8 @@ static void timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) TIM_InitTimBaseStruct(&TIM_TimeBaseStructure); TIM_TimeBaseStructure.Period = 10000 - 1; - ; TIM_TimeBaseStructure.Prescaler = prescaler_value; - TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1; if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_UP) { @@ -540,11 +539,11 @@ static void timer_stop(rt_clock_timer_t *timer) static rt_err_t timer_ctrl(rt_clock_timer_t *timer, rt_uint32_t cmd, void *arg) { - struct n32_clock_timer *tim_device = RT_NULL; - rt_err_t result = -RT_ERROR; - uint32_t prescaler_value = 0; - rt_uint32_t tim_div; - RCC_ClocksTypeDef RCC_Clocks; + struct n32_clock_timer *tim_device = RT_NULL; + rt_err_t result = -RT_ERROR; + uint32_t prescaler_value = 0; + rt_uint32_t tim_div; + RCC_ClocksTypeDef RCC_Clocks; RT_ASSERT(timer != RT_NULL); RT_ASSERT(arg != RT_NULL); @@ -616,11 +615,11 @@ static rt_uint32_t timer_counter_get(rt_clock_timer_t *timer) static const struct rt_clock_timer_info _info = TIM_DEV_INFO_CONFIG; static const struct rt_clock_timer_ops _ops = { - .init = timer_init, - .start = timer_start, - .stop = timer_stop, + .init = timer_init, + .start = timer_start, + .stop = timer_stop, .count_get = timer_counter_get, - .control = timer_ctrl, + .control = timer_ctrl, }; #ifdef BSP_USING_ATIM1 @@ -877,13 +876,13 @@ void BTIM4_IRQHandler(void) static int n32_clock_timer_init(void) { - rt_uint32_t i = 0; - int result = RT_EOK; + rt_uint32_t i = 0; + int result = RT_EOK; for (i = 0; i < sizeof(n32_clock_timer_obj) / sizeof(n32_clock_timer_obj[0]); i++) { n32_clock_timer_obj[i].time_device.info = &_info; - n32_clock_timer_obj[i].time_device.ops = &_ops; + n32_clock_timer_obj[i].time_device.ops = &_ops; if (rt_clock_timer_register(&n32_clock_timer_obj[i].time_device, n32_clock_timer_obj[i].name, RT_NULL) == RT_EOK) { diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/.config b/bsp/n32/n32hxxx/n32h760zil7-stb/.config index 30312c895c5..e495a65abe9 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/.config +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/.config @@ -1486,6 +1486,8 @@ CONFIG_SOC_SERIES_N32H7xx=y # # Onboard Peripheral Drivers # +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_LCD is not set # CONFIG_BSP_USING_ETH is not set # end of Onboard Peripheral Drivers @@ -1500,7 +1502,7 @@ CONFIG_BSP_USING_UART1=y # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_SPI is not set -# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SOFT_I2C is not set # CONFIG_BSP_USING_HARD_I2C is not set # CONFIG_BSP_USING_ONCHIP_RTC is not set # CONFIG_BSP_USING_ADC is not set diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx index b5de00848eb..506b1fb808b 100644 Binary files a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx and b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/Cube.ntfx differ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h index ee919a8a8fb..8015ca89bd3 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/inc/n32h7xx_cfg.h @@ -29,7 +29,7 @@ extern "C" { /* NTFx CODE START Extern*/ extern void SysTick_Delayms(uint32_t Delayms); -extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); +extern void DMA_SetPerMemAddr(DMA_ChannelType *DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize); extern bool RCC_Configuration(void); extern bool NVIC_Configuration(void); extern bool DMA_Configuration(void); diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c index e59369ba848..94f7dfe3749 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Cube_Config/USER/src/n32h7xx_cfg.c @@ -19,60 +19,60 @@ void SysTick_Delayms(uint32_t Delayms) { } } -/** -*@name DMA_SetSrcDstAddr. -*@brief Set peripher address and memory address of DMA -*param DMAy (The input parameters must be the following values): -* - DMA1 -* - DMA2 -* - DMA3 -*param ChNum (The input parameters must be the following values): -* - DMA_CHANNEL_0 -* - DMA_CHANNEL_1 -* - DMA_CHANNEL_2 -* - DMA_CHANNEL_3 -* - DMA_CHANNEL_4 -* - DMA_CHANNEL_5 -* - DMA_CHANNEL_6 -* - DMA_CHANNEL_7 -*@param SrcAddr Source address -*@param DstAddr Destination address -*@return status -*/ -void DMA_SetSrcDstAddr(DMA_Module *const DMAy, DMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) + /** + *@name DMA_SetSrcDstAddr. + *@brief Set peripher address and memory address of DMA + *param DMAy (The input parameters must be the following values): + * - DMA1 + * - DMA2 + * - DMA3 + *param ChNum (The input parameters must be the following values): + * - DMA_CHANNEL_0 + * - DMA_CHANNEL_1 + * - DMA_CHANNEL_2 + * - DMA_CHANNEL_3 + * - DMA_CHANNEL_4 + * - DMA_CHANNEL_5 + * - DMA_CHANNEL_6 + * - DMA_CHANNEL_7 + *@param SrcAddr Source address + *@param DstAddr Destination address + *@return status + */ +void DMA_SetSrcDstAddr(DMA_Module * const DMAy, DMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) { /* Sets channel n source address register */ WRITE_REG(DMAy->CH[ChNum].SA, SrcAddr); /* Sets channel n destination address register */ WRITE_REG(DMAy->CH[ChNum].DA, DstAddr); } -/** -*@name MDMA_SetSrcDstAddr. -*@brief Set peripher address and memory address of MDMA -*param MDMAy (The input parameters must be the following values): -* - MDMA -*param ChNum (The input parameters must be the following values): -* - MDMA_CHANNEL_0 -* - MDMA_CHANNEL_1 -* - MDMA_CHANNEL_2 -* - MDMA_CHANNEL_3 -* - MDMA_CHANNEL_4 -* - MDMA_CHANNEL_5 -* - MDMA_CHANNEL_6 -* - MDMA_CHANNEL_7 -* - MDMA_CHANNEL_8 -* - MDMA_CHANNEL_9 -* - MDMA_CHANNEL_10 -* - MDMA_CHANNEL_11 -* - MDMA_CHANNEL_12 -* - MDMA_CHANNEL_13 -* - MDMA_CHANNEL_14 -* - MDMA_CHANNEL_15 -*@param SrcAddr Source address -*@param DstAddr Destination address -*@return status -*/ -void MDMA_SetSrcDstAddr(MDMA_Module *const MDMAy, MDMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) + /** + *@name MDMA_SetSrcDstAddr. + *@brief Set peripher address and memory address of MDMA + *param MDMAy (The input parameters must be the following values): + * - MDMA + *param ChNum (The input parameters must be the following values): + * - MDMA_CHANNEL_0 + * - MDMA_CHANNEL_1 + * - MDMA_CHANNEL_2 + * - MDMA_CHANNEL_3 + * - MDMA_CHANNEL_4 + * - MDMA_CHANNEL_5 + * - MDMA_CHANNEL_6 + * - MDMA_CHANNEL_7 + * - MDMA_CHANNEL_8 + * - MDMA_CHANNEL_9 + * - MDMA_CHANNEL_10 + * - MDMA_CHANNEL_11 + * - MDMA_CHANNEL_12 + * - MDMA_CHANNEL_13 + * - MDMA_CHANNEL_14 + * - MDMA_CHANNEL_15 + *@param SrcAddr Source address + *@param DstAddr Destination address + *@return status + */ +void MDMA_SetSrcDstAddr(MDMA_Module * const MDMAy, MDMA_ChNumType ChNum, uint32_t SrcAddr, uint32_t DstAddr) { /* Sets channel n source address register */ WRITE_REG(MDMAy->CH[ChNum].SA, SrcAddr); @@ -95,7 +95,8 @@ bool RCC_Configuration(void) RCC_EnableHsi(ENABLE); /* Wait till HSI is ready */ ClockStatus = RCC_WaitHsiStable(); - if (ClockStatus != SUCCESS) return false; + if (ClockStatus != SUCCESS) + return false; RCC_ConfigSysclkDivider(RCC_SYSCLK_DIV1); RCC_ConfigSysbusDivider(RCC_BUSCLK_DIV2); /*Configures the Periph clock source as HSI*/ @@ -124,7 +125,8 @@ bool RCC_Configuration(void) /* configure sys_clk source is PLL1A */ RCC_ConfigSysclk(RCC_SYSCLK_SRC_PLL1A); /* Check if sys_clk source is PLL1A */ - while (RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A); + while (RCC_GetSysclkSrc() != RCC_SYSCLK_STS_PLL1A) + ; /*Config the USART1/2 PCLK divider from ahb1*/ RCC_ConfigUSARTPClk(RCC_USARTPCLK_AHB1_DIV1); @@ -135,7 +137,7 @@ bool RCC_Configuration(void) /*Enables the APB1 peripheral clock 3 .*/ RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1, ENABLE); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } @@ -147,8 +149,7 @@ bool RCC_Configuration(void) */ bool NVIC_Configuration(void) { - - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } @@ -160,8 +161,7 @@ bool NVIC_Configuration(void) */ bool DMA_Configuration(void) { - - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } @@ -173,7 +173,6 @@ bool DMA_Configuration(void) */ bool GPIO_Configuration(void) { - GPIO_InitType GPIO_InitStructure; GPIO_InitStruct(&GPIO_InitStructure); /* Enable the GPIO clock*/ @@ -182,22 +181,22 @@ bool GPIO_Configuration(void) /*Initialize input GPIO */ - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; - GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Alternate = GPIO_AF5; - GPIO_InitStructure.Pin = GPIO_PIN_10; + GPIO_InitStructure.Pin = GPIO_PIN_10; GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); /*Initialize AF_PP GPIO */ - GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; - GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; + GPIO_InitStructure.GPIO_Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.GPIO_Pull = GPIO_PULL_UP; GPIO_InitStructure.GPIO_Slew_Rate = GPIO_SLEW_RATE_SLOW; - GPIO_InitStructure.GPIO_Current = GPIO_DC_2mA; + GPIO_InitStructure.GPIO_Current = GPIO_DC_2mA; GPIO_InitStructure.GPIO_Alternate = GPIO_AF7; - GPIO_InitStructure.Pin = GPIO_PIN_9; + GPIO_InitStructure.Pin = GPIO_PIN_9; GPIO_InitPeripheral(GPIOA, &GPIO_InitStructure); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } @@ -215,20 +214,20 @@ bool USART_Configuration(void) /*********initialize the USART1************/ USART_DeInit(USART1); - USART_InitStructure.BaudRate = 115200; - USART_InitStructure.WordLength = USART_WL_8B; - USART_InitStructure.StopBits = USART_STPB_1; - USART_InitStructure.Parity = USART_PE_NO; + USART_InitStructure.BaudRate = 115200; + USART_InitStructure.WordLength = USART_WL_8B; + USART_InitStructure.StopBits = USART_STPB_1; + USART_InitStructure.Parity = USART_PE_NO; USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE; - USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; - USART_InitStructure.OverSampling = USART_16OVER ; + USART_InitStructure.Mode = USART_MODE_RX | USART_MODE_TX; + USART_InitStructure.OverSampling = USART_16OVER; /* Configure USART1 */ USART_Init(USART1, &USART_InitStructure); /* Enable the USART1 */ USART_Enable(USART1, ENABLE); - /* NTFx CODE END */ +/* NTFx CODE END */ return true; } diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig index 206c291e661..11e389d40d4 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/Kconfig @@ -2,6 +2,177 @@ menu "Hardware Drivers Config" menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_SDRAM + bool "Enable SDRAM" + default n + if BSP_USING_SDRAM + choice BSP_SDRAM_BANK_SEL + prompt "Select SDRAM Bank" + default BSP_SDRAM_BANK1 + + config BSP_SDRAM_BANK1 + bool "Select SDRAM Bank1" + + config BSP_SDRAM_BANK2 + bool "Select SDRAM Bank2" + endchoice + + choice BSP_SDRAM_DATA_WIDTH_SEL + prompt "Select SDRAM Data Width" + default BSP_SDRAM_DATA_WIDTH_32 + + config BSP_SDRAM_DATA_WIDTH_8 + bool "SDRAM Data Width 8-bits" + + config BSP_SDRAM_DATA_WIDTH_16 + bool "SDRAM Data Width 16-bits" + + config BSP_SDRAM_DATA_WIDTH_32 + bool "SDRAM Data Width 32-bits" + endchoice + + choice BSP_SDRAM_COLUMN_BITS_SEL + prompt "Select SDRAM Column Bits" + default BSP_SDRAM_COLUMN_BIT_9 + + config BSP_SDRAM_COLUMN_BIT_8 + bool "SDRAM SDRAM Column Bits 8-bits" + + config BSP_SDRAM_COLUMN_BIT_9 + bool "SDRAM SDRAM Column Bits 9-bits" + + config BSP_SDRAM_COLUMN_BIT_10 + bool "SDRAM SDRAM Column Bits 10-bits" + + config BSP_SDRAM_COLUMN_BIT_11 + bool "SDRAM SDRAM Column Bits 11-bits" + endchoice + + choice BSP_SDRAM_ROW_BITS_SEL + prompt "Select SDRAM Row Bits" + default BSP_SDRAM_ROW_BIT_12 + + config BSP_SDRAM_ROW_BIT_11 + bool "SDRAM SDRAM Row Bits 11-bits" + + config BSP_SDRAM_ROW_BIT_12 + bool "SDRAM SDRAM Row Bits 12-bits" + + config BSP_SDRAM_ROW_BIT_13 + bool "SDRAM SDRAM Row Bits 13-bits" + endchoice + + choice BSP_SDRAM_CAS_LATENCY_SEL + prompt "Select SDRAM CAS Latency" + default BSP_SDRAM_CAS_LATENCY_3 + + config BSP_SDRAM_CAS_LATENCY_1 + bool "SDRAM SDRAM CAS Latency 1" + + config BSP_SDRAM_CAS_LATENCY_2 + bool "SDRAM SDRAM CAS Latency 2" + + config BSP_SDRAM_CAS_LATENCY_3 + bool "SDRAM SDRAM CAS Latency 3" + endchoice + + config BSP_SDRAM_SIZE + int "SDARM Size (MBytes)" + range 8 256 + default 32 + endif + + menuconfig BSP_USING_LCD + bool "Enable ATK-MD0700R-800480, 5 inch screen, 800 * 480, RGB565 LCD" + select BSP_USING_LCDC + select BSP_USING_SDRAM + default n + if BSP_USING_LCD + config BSP_BITS_PER_PIXEL + int "LCD Bits Per Pixel" + default 16 + + choice BSP_LCD_PIXEL_FORMAT_SEL + prompt "Select LCD PIXEL FORMAT" + default BSP_LCD_PIXEL_FORMAT_RGB565 + + config BSP_LCD_PIXEL_FORMAT_RGB565 + bool "SDRAM LCD Pixel Format RGB565" + + config BSP_LCD_PIXEL_FORMAT_ARGB8888 + bool "SDRAM LCD Pixel Format ARGB8888" + + config BSP_LCD_PIXEL_FORMAT_RGB888 + bool "SDRAM LCD Pixel Format RGB888" + endchoice + + config BSP_LCD_WIDTH_PIXEL + int "LCD Width Pixel" + default 800 + + config BSP_LCD_HEIGHT_PIXEL + int "LCD Heigh Pixel" + default 480 + + config BSP_LCD_HSYNC_WIDTH_PIXEL + int "LCD Hsync Width Pixel" + default 34 + + config BSP_LCD_VSYNC_HEIGHT_PIXEL + int "LCD Vsync Heigh Pixel" + default 10 + + config BSP_LCD_HBP_PIXEL + int "LCD HBP Pixel" + default 46 + + config BSP_LCD_VBP_PIXEL + int "LCD VBP Pixel" + default 23 + + config BSP_LCD_HFP_PIXEL + int "LCD HFP Pixel" + default 210 + + config BSP_LCD_VFP_PIXEL + int "LCD VFP Pixel" + default 22 + + choice BSP_LCD_BACKLIGHT_SEL + prompt "Select LCD BACKLIGHT Control Type" + default BSP_LCD_BACKLIGHT_USING_GPIO + + config BSP_LCD_BACKLIGHT_USING_GPIO + bool "LCD BACKLIGHT Using GPIO Control" + + config BSP_LCD_BACKLIGHT_USING_PWM + bool "LCD BACKLIGHT Using PWM Control" + select RT_USING_PWM + select BSP_USING_PWM + endchoice + + if BSP_LCD_BACKLIGHT_USING_GPIO + config BSP_LCD_BACKLIGHT_PIN + int "Backlight GPIO Port" + default 115 + + config BSP_LCD_DISPLAY_PIN + int "Display GPIO Pin" + default 26 + endif + + if BSP_LCD_BACKLIGHT_USING_PWM + config BSP_LCD_PWM_DEV_NAME + string "PWM Device Name" + default "pwm1" + + config BSP_LCD_PWM_DEV_CHANNEL + int "PWM Channel" + default 1 + endif + endif + + menuconfig BSP_USING_ETH bool "Enable Ethernet" default n diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sdram_port.h b/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sdram_port.h new file mode 100644 index 00000000000..d17b34a7729 --- /dev/null +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/board/ports/sdram_port.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2006-2025, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2025-07-21 ox-horse first version for N32H760ZIL7-STB (W9825G6KH-6) + */ +/* + * SDRAM Chip: IS42S32800J + * 4 Banks x 2M words x 32 bits = 32 MB + * 12 row address bits, 9 column address bits + * + * + * N32H760 SDRAM Controller: + * SDRAM1 base: 0xC0000000 (can remap to 0x60000000) + * SDRAM2 base: 0xD0000000 + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +#include "board.h" + +/*============================================================================ + * Part 0: N32cube SDRAM clock and GPIO Configuration + *============================================================================*/ +/* clock config in RCC_Configuration()*/ +/* gpio config in GPIO_Configuration()*/ + +/*============================================================================ + * Part 1: SDRAM Device Configuration + *============================================================================*/ + +/* Bank select: 1 = SDRAM1 (0xC0000000), 2 = SDRAM2 (0xD0000000) */ +#ifdef BSP_SDRAM_BANK1 +#define SDRAM_BANK_ADDR ((uint32_t)0xC0000000) +#endif /* BSP_SDRAM_BANK1 */ +#ifdef BSP_SDRAM_BANK2 +#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) +#endif /* BSP_SDRAM_BANK2 */ + +/* Data bus width: 8 / 16 / 32 */ +#ifdef BSP_SDRAM_DATA_WIDTH_8 +#define SDRAM_DATA_WIDTH 8 +#endif /* BSP_SDRAM_DATA_WIDTH_8 */ +#ifdef BSP_SDRAM_DATA_WIDTH_16 +#define SDRAM_DATA_WIDTH 16 +#endif /* BSP_SDRAM_DATA_WIDTH_16 */ +#ifdef BSP_SDRAM_DATA_WIDTH_32 +#define SDRAM_DATA_WIDTH 32 +#endif /* BSP_SDRAM_DATA_WIDTH_32 */ + + +/* Column address bits: 8-256 / 9-512 / 10-1024 / 11-2048 */ +#ifdef BSP_SDRAM_COLUMN_BIT_8 +#define SDRAM_COLUMN_BITS 8 +#endif /* BSP_SDRAM_COLUMN_BIT_8 */ +#ifdef BSP_SDRAM_COLUMN_BIT_9 +#define SDRAM_COLUMN_BITS 9 +#endif /* BSP_SDRAM_COLUMN_BIT_9 */ +#ifdef BSP_SDRAM_COLUMN_BIT_10 +#define SDRAM_COLUMN_BITS 10 +#endif /* BSP_SDRAM_COLUMN_BIT_10 */ +#ifdef BSP_SDRAM_COLUMN_BIT_11 +#define SDRAM_COLUMN_BITS 11 +#endif /* BSP_SDRAM_COLUMN_BIT_11 */ + +/* Row address bits: 11-2048 / 12-4096 / 13-8192 */ +#ifdef BSP_SDRAM_ROW_BIT_11 +#define SDRAM_ROW_BITS 11 +#endif /* BSP_SDRAM_ROW_BIT_11 */ +#ifdef BSP_SDRAM_ROW_BIT_12 +#define SDRAM_ROW_BITS 12 +#endif /* BSP_SDRAM_ROW_BIT_12 */ +#ifdef BSP_SDRAM_ROW_BIT_13 +#define SDRAM_ROW_BITS 13 +#endif /* BSP_SDRAM_ROW_BIT_13 */ + +/* Address mask for device chip-select matching */ +#define SDRAM_ADDRESS_MASK ((uint32_t)(0xFFFFFFFF - ((BSP_SDRAM_SIZE * 1024U * 1024U) - 1))) + +/*============================================================================ + * Part 2: Timing Parameters (unit: SDRAM clock cycles) + * All values below assume SDRAM clock = 100 MHz (tCK = 10 ns). + * Recalculate when using a different SDRAM frequency. + *============================================================================*/ + +/* tRAS: Row Active Time (min 42ns → ceil(42/10) = 5) */ +#define SELFREFRESHTIME 7 + +/* tRC: Row Cycle Time (min 60ns → ceil(60/10) = 6) */ +#define ROWCYCLEDELAY 9 + +/* tRP: Precharge Time (min 18ns → ceil(18/10) = 2) */ +#define RPDELAY 4 + +/* tWR: Write Recovery (min 12ns → ceil(12/10) = 2) */ +#define WRITERECOVERYTIME 3 + +/* tRCD: RAS to CAS Delay (min 18ns → ceil(18/10) = 2) */ +#define RCDDELAY 4 + +/* tRRD: Row Activate to Row Activate delay (min 12ns → ceil(12/10) = 2) */ +#define SDRAM_RP_DELAY 3 + +/* tRFC: Refresh Cycle Time (min 67.5ns for 256Mb → ceil(67.5/10) = 7) */ +#define SDRAM_REFRESH_CYCLE 9 + +/* Auto-refresh interval counter value + * Formula: RefreshInterval = SDRAM_CLK_MHz * tREF_ms * 1000 / Nrows + * For example: SDRAM_CLK=133MHz, tREF=64ms, rows=4096: + * = 133 * 64 * 1000 / 4096 ≈ 0x07A1 + * Adjust based on actual SDRAMMEMCLK configuration. */ +#define SDRAM_REFRESH_COUNT ((uint32_t)0x0750) /* whichever is smaller */ + +/*============================================================================ + * Part 3: SDRAM Chip Mode Register Value (sent via LOADMODE command) + * These macros are also defined internally in drv_sdram.c. + *============================================================================*/ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +#endif /* __SDRAM_PORT_H__ */ diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx index d4cb02535c5..8646d492b6e 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvoptx @@ -181,4 +181,1020 @@ + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 5 + 2 + 0 + 0 + 0 + ..\..\..\..\libcpu\arm\cortex-m7\context_rvds.S + context_rvds.S + 0 + 0 + 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mem.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\src\object.c + object.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\src\scheduler_comm.c + scheduler_comm.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libc + 0 + 0 + 0 + 0 + + 8 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 8 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 8 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 8 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 8 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + 8 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 8 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 8 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 8 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 9 + 66 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\misc.c + misc.c + 0 + 0 + + + 9 + 67 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_gpio.c + n32h7xx_gpio.c + 0 + 0 + + + 9 + 68 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_mmu.c + n32h7xx_mmu.c + 0 + 0 + + + 9 + 69 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dma.c + n32h7xx_dma.c + 0 + 0 + + + 9 + 70 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dmamux.c + n32h7xx_dmamux.c + 0 + 0 + + + 9 + 71 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_pwr.c + n32h7xx_pwr.c + 0 + 0 + + + 9 + 72 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_rcc.c + n32h7xx_rcc.c + 0 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dbg.c + n32h7xx_dbg.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_exti.c + n32h7xx_exti.c + 0 + 0 + + + 9 + 75 + 1 + 0 + 0 + 0 + packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_usart.c + n32h7xx_usart.c + 0 + 0 + + + + + Libraries-CMSIS + 0 + 0 + 0 + 0 + + 10 + 76 + 1 + 0 + 0 + 0 + packages\n32h7xx_cmsis_driver-latest\device\system_n32h7xx.c + system_n32h7xx.c + 0 + 0 + + + 10 + 77 + 2 + 0 + 0 + 0 + packages\n32h7xx_cmsis_driver-latest\device\startup\startup_n32h73x_76x.s + startup_n32h73x_76x.s + 0 + 0 + + + 10 + 78 + 1 + 0 + 0 + 0 + packages\n32h7xx_cmsis_driver-latest\device\soc_mdk.c + soc_mdk.c + 0 + 0 + + + diff --git a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx index db303dddbdf..d0e5eb56e71 100644 --- a/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx +++ b/bsp/n32/n32hxxx/n32h760zil7-stb/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread @@ -16,28 +19,28 @@ Nationstech.N32H7xx_DFP.1.2.0 http://www.keil.com/pack/ IRAM(0x24000000,0x20000) IROM(0x15000000,0x1E0000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD24000000 -FC8000 -FN1 -FF0N32H76x_2048 -FS015000000 -FL01E0000 -FP0($$Device:N32H760xIx7$Flash\N32H76x_2048.FLM)) 0 $$Device:N32H760xIx7$firmware\CMSIS\device\N32H76x.h - - - - - - - - - + + + + + + + + + $$Device:N32H760xIx7$svd\N32H76x.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M7" - + 0 0 0 @@ -306,7 +309,7 @@ 0x0 - + 1 @@ -333,10 +336,10 @@ 0 0 - - USING_TCM, __DCACHE_PRESENT=1, RT_USING_LIBC, __STDC_LIMIT_MACROS, CORE_CM7, N32H76x, __RTTHREAD__, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, __ICACHE_PRESENT=1, __CLK_TCK=RT_TICK_PER_SECOND - - board;..\libraries\N32_Drivers\drivers;..\..\..\..\libcpu\arm\cortex-m7;applications;..\..\..\..\libcpu\arm\common;..\..\..\..\components\libc\posix\io\poll;..\libraries\N32_Drivers\drivers\config;packages\n32h7xx_cmsis_driver-latest\device;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\epoll;.;board\Cube_Config\USER\inc;..\..\..\..\components\finsh;..\..\..\..\components\net\utest;..\..\..\..\components\drivers\smp_call;..\..\..\..\include;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\phy;..\..\..\..\components\libc\posix\ipc;..\..\..\..\components\drivers\include;packages\CMSIS-Core-latest\Include;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\N32_Drivers;..\..\..\..\components\drivers\include;packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\inc;..\..\..\..\components\libc\compilers\common\extension;..\..\..\..\components\drivers\include;..\..\..\..\components\libc\compilers\common\include;board\ports;..\..\..\..\components\drivers\include + + N32H76x, RT_USING_LIBC, __ICACHE_PRESENT=1, __CLK_TCK=RT_TICK_PER_SECOND, __DCACHE_PRESENT=1, CORE_CM7, USE_STDPERIPH_DRIVER, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, USING_TCM, __RTTHREAD__ + + ..\..\..\..\components\drivers\phy;..\..\..\..\components\drivers\include;..\..\..\..\include;board;..\..\..\..\components\libc\posix\ipc;..\libraries\N32_Drivers\drivers\config;..\..\..\..\components\libc\posix\io\eventfd;..\..\..\..\components\drivers\include;..\..\..\..\components\dfs\dfs_v1\include;applications;..\..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\..\components\libc\compilers\common\include;board\ports;..\..\..\..\components\drivers\smp_call;..\..\..\..\components\drivers\include;..\..\..\..\components\drivers\include;..\..\..\..\components\net\utest;board\Cube_Config\USER\inc;..\..\..\..\libcpu\arm\cortex-m7;..\..\..\..\components\drivers\include;packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\inc;..\..\..\..\components\libc\posix\io\poll;..\..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\..\..\components\drivers\include;packages\CMSIS-Core-latest\Include;packages\n32h7xx_cmsis_driver-latest\device;..\..\..\..\components\libc\posix\io\epoll;..\..\..\..\libcpu\arm\common;..\libraries\N32_Drivers;..\..\..\..\components\finsh;..\libraries\N32_Drivers\drivers;..\..\..\..\components\libc\compilers\common\extension;. @@ -351,10 +354,10 @@ 0 4 - - - - + + + + @@ -366,13 +369,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - + + --entry Reset_Handler - - + + @@ -395,36 +398,26 @@ 1 ..\..\..\..\libcpu\arm\common\atomic_arm.c - - div0.c 1 ..\..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\..\libcpu\arm\cortex-m7\context_rvds.S - - cpu_cache.c 1 ..\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c - - cpuport.c 1 @@ -440,222 +433,668 @@ 1 ..\..\..\..\components\drivers\core\device.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - completion_comm.c 1 ..\..\..\..\components\drivers\ipc\completion_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - completion_up.c 1 ..\..\..\..\components\drivers\ipc\completion_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - condvar.c 1 ..\..\..\..\components\drivers\ipc\condvar.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - dataqueue.c 1 ..\..\..\..\components\drivers\ipc\dataqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - pipe.c 1 ..\..\..\..\components\drivers\ipc\pipe.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringblk_buf.c 1 ..\..\..\..\components\drivers\ipc\ringblk_buf.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringbuffer.c 1 ..\..\..\..\components\drivers\ipc\ringbuffer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - waitqueue.c 1 ..\..\..\..\components\drivers\ipc\waitqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - workqueue.c 1 ..\..\..\..\components\drivers\ipc\workqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - dev_pin.c 1 ..\..\..\..\components\drivers\pin\dev_pin.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - dev_serial.c 1 ..\..\..\..\components\drivers\serial\dev_serial.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + @@ -671,29 +1110,21 @@ 1 ..\libraries\N32_Drivers\drivers\drv_gpio.c - - drv_usart.c 1 ..\libraries\N32_Drivers\drivers\drv_usart.c - - drv_common.c 1 ..\libraries\N32_Drivers\drv_common.c - - n32h7xx_cfg.c 1 board\Cube_Config\USER\src\n32h7xx_cfg.c - - board.c 1 @@ -701,6 +1132,459 @@ + + Filesystem + + + devfs.c + 1 + ..\..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + dfs_elm.c + 1 + ..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + ff.c + 1 + ..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + ffunicode.c + 1 + ..\..\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + dfs.c + 1 + ..\..\..\..\components\dfs\dfs_v1\src\dfs.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + dfs_file.c + 1 + ..\..\..\..\components\dfs\dfs_v1\src\dfs_file.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + dfs_fs.c + 1 + ..\..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + dfs_posix.c + 1 + ..\..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + --c99 + + + + + + + + + + Finsh @@ -709,27 +1593,26 @@ 1 ..\..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\..\components\finsh\msh_parse.c - - cmd.c 1 ..\..\..\..\components\finsh\cmd.c + + msh_file.c + 1 + ..\..\..\..\components\finsh\msh_file.c + @@ -740,279 +1623,836 @@ 1 ..\..\..\..\src\clock.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - components.c 1 ..\..\..\..\src\components.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - cpu_up.c 1 ..\..\..\..\src\cpu_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - defunct.c 1 ..\..\..\..\src\defunct.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - idle.c 1 ..\..\..\..\src\idle.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - ipc.c 1 ..\..\..\..\src\ipc.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - irq.c 1 ..\..\..\..\src\irq.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kservice.c 1 ..\..\..\..\src\kservice.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mem.c 1 ..\..\..\..\src\mem.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mempool.c 1 ..\..\..\..\src\mempool.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - object.c 1 ..\..\..\..\src\object.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_comm.c 1 ..\..\..\..\src\scheduler_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_up.c 1 ..\..\..\..\src\scheduler_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - thread.c 1 ..\..\..\..\src\thread.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - timer.c 1 ..\..\..\..\src\timer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + @@ -1028,85 +2468,61 @@ 1 ..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\..\components\libc\compilers\common\cctype.c - - cstdlib.c 1 ..\..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\..\components\libc\compilers\common\ctime.c - - cunistd.c 1 ..\..\..\..\components\libc\compilers\common\cunistd.c - - cwchar.c 1 ..\..\..\..\components\libc\compilers\common\cwchar.c - - kerrno.c 1 ..\..\..\..\src\klibc\kerrno.c - - kstdio.c 1 ..\..\..\..\src\klibc\kstdio.c - - kstring.c 1 ..\..\..\..\src\klibc\kstring.c - - rt_vsnprintf_tiny.c 1 ..\..\..\..\src\klibc\rt_vsnprintf_tiny.c - - rt_vsscanf.c 1 @@ -1122,64 +2538,46 @@ 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\misc.c - - n32h7xx_gpio.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_gpio.c - - n32h7xx_mmu.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_mmu.c - - n32h7xx_dma.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dma.c - - n32h7xx_dmamux.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dmamux.c - - n32h7xx_pwr.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_pwr.c - - n32h7xx_rcc.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_rcc.c - - n32h7xx_dbg.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_dbg.c - - n32h7xx_exti.c 1 packages\n32h7xx_std_driver-latest\n32h7xx_std_periph_driver\src\n32h7xx_exti.c - - n32h7xx_usart.c 1 @@ -1195,15 +2593,11 @@ 1 packages\n32h7xx_cmsis_driver-latest\device\system_n32h7xx.c - - startup_n32h73x_76x.s 2 packages\n32h7xx_cmsis_driver-latest\device\startup\startup_n32h73x_76x.s - - soc_mdk.c 1 @@ -1214,9 +2608,20 @@ + - - - + + + + + + + + project + 1 + + + +