Rename atomic.notify and *.atomic.wait (#149)

The new names are memory.atomic.notify, memory.atomic.wait32, and
memory.atomic.wait64.

See #145.

Author: binji

document/core/appendix/index-instructions.rst

@@ -200,8 +200,8 @@ Instruction                                                  Binary Opcode
 :math:`\F32.\REINTERPRET\K{\_}\I32`                          :math:`\hex{BE}`           :math:`[\I32] \to [\F32]`                   :ref:`validation <valid-cvtop>`                :ref:`execution <exec-cvtop>`, :ref:`operator <op-reinterpret>`
 :math:`\F64.\REINTERPRET\K{\_}\I64`                          :math:`\hex{BF}`           :math:`[\I64] \to [\F64]`                   :ref:`validation <valid-cvtop>`                :ref:`execution <exec-cvtop>`, :ref:`operator <op-reinterpret>`
 :math:`\ATOMICNOTIFY~\memarg`                                :math:`\hex{FE}~\hex{00}`  :math:`[\I32~\I64] \to [\I64]`              :ref:`validation <valid-atomic-notify>`
-:math:`\I32.\ATOMICWAIT~\memarg`                             :math:`\hex{FE}~\hex{01}`  :math:`[\I32~\I32~\I64] \to [\I32]`         :ref:`validation <valid-atomic-wait>`
-:math:`\I64.\ATOMICWAIT~\memarg`                             :math:`\hex{FE}~\hex{02}`  :math:`[\I32~\I64~\I64] \to [\I32]`         :ref:`validation <valid-atomic-wait>`
+:math:`\MEMORYATOMICWAIT32~\memarg`                          :math:`\hex{FE}~\hex{01}`  :math:`[\I32~\I32~\I64] \to [\I32]`         :ref:`validation <valid-atomic-wait>`
+:math:`\MEMORYATOMICWAIT64~\memarg`                          :math:`\hex{FE}~\hex{02}`  :math:`[\I32~\I64~\I64] \to [\I32]`         :ref:`validation <valid-atomic-wait>`
 :math:`\I32.\ATOMICLOAD~\memarg`                             :math:`\hex{FE}~\hex{10}`  :math:`[\I32] \to [\I32]`                   :ref:`validation <valid-atomic-load>`          :ref:`execution <exec-atomic-load>`
 :math:`\I64.\ATOMICLOAD~\memarg`                             :math:`\hex{FE}~\hex{11}`  :math:`[\I32] \to [\I64]`                   :ref:`validation <valid-atomic-load>`          :ref:`execution <exec-atomic-load>`
 :math:`\I32.\ATOMICLOAD\K{8\_u}~\memarg`                     :math:`\hex{FE}~\hex{12}`  :math:`[\I32] \to [\I32]`                   :ref:`validation <valid-atomic-loadn>`         :ref:`execution <exec-atomic-loadn>`

document/core/binary/instructions.rst

@@ -184,9 +184,9 @@ Each variant of :ref:`atomic memory instruction <syntax-instr-atomic-memory>` is
 .. math::
    \begin{array}{llclll}
    \production{instruction} & \Binstr &::=& \dots && \phantom{thisshouldbeenough} \\ &&|&
-     \hex{FE}~\hex{00}~~m{:}\Bmemarg &\Rightarrow& \ATOMICNOTIFY~m \\ &&|&
-     \hex{FE}~\hex{01}~~m{:}\Bmemarg &\Rightarrow& \I32.\ATOMICWAIT~m \\ &&|&
-     \hex{FE}~\hex{02}~~m{:}\Bmemarg &\Rightarrow& \I64.\ATOMICWAIT~m \\
+     \hex{FE}~\hex{00}~~m{:}\Bmemarg &\Rightarrow& \MEMORYATOMICNOTIFY~m \\ &&|&
+     \hex{FE}~\hex{01}~~m{:}\Bmemarg &\Rightarrow& \MEMORYATOMICWAIT\K{32}~m \\ &&|&
+     \hex{FE}~\hex{02}~~m{:}\Bmemarg &\Rightarrow& \MEMORYATOMICWAIT\K{64}~m \\
    \end{array}
 
 

document/core/exec/instructions.rst

@@ -966,46 +966,46 @@ See :ref:`above <exec-atomic-store>`.
 
 .. _exec-wait:
 
-:math:`t\K{.}\ATOMICWAIT`
-.........................
+:math:`\MEMORYATOMICWAIT{N}`
+............................
 
 .. todo:: update to new rules
 .. todo:: add text
 
 .. math::
    \begin{array}{l}
    \begin{array}{lcl@{\qquad}l}
-   F; (\I64.\CONST~k)~(t.\CONST~c)~(\I32.\CONST~i)~t.\ATOMICWAIT
-     &\stepto^{(\ARD~a.\LLEN~n)~(\ARD~a.\LDATA[i]~b^{|t|})}&
+   F; (\I64.\CONST~k)~(\iN.\CONST~c)~(\I32.\CONST~i)~\MEMORYATOMICWAIT{N}
+     &\stepto^{(\ARD~a.\LLEN~n)~(\ARD~a.\LDATA[i]~b^{N})}&
      F; (\WAITX~a.\LDATA[i])
    \end{array}
    \\ \qquad
      \begin{array}[t]{@{}r@{~}l@{}}
-     (\iff & \X{ea} + |t|/8 \leq n \\
-     \wedge & \X{ea} \mod |t|/8 = 0 \\
-     \wedge & b^{|t|} = \bytes_t(c) \\
+     (\iff & \X{ea} + N/8 \leq n \\
+     \wedge & \X{ea} \mod N/8 = 0 \\
+     \wedge & b^{N} = \bytes_t(c) \\
      \end{array}
    \\[1ex]
    \begin{array}{lcl@{\qquad}l}
-   F; (\I64.\CONST~k)~(t.\CONST~c)~(\I32.\CONST~i)~t.\ATOMICWAIT
-     &\stepto^{(\ARD~a.\LLEN~n)~(\ARD~a.\LDATA[i]~b^{|t|})}&
+   F; (\I64.\CONST~k)~(\iN.\CONST~c)~(\I32.\CONST~i)~\MEMORYATOMICWAIT{N}
+     &\stepto^{(\ARD~a.\LLEN~n)~(\ARD~a.\LDATA[i]~b^{N})}&
      F; (\I32.\CONST~1)
    \end{array}
    \\ \qquad
      \begin{array}[t]{@{}r@{~}l@{}}
-     (\iff & \X{ea} + |t|/8 \leq n \\
-     \wedge & \X{ea} \mod |t|/8 = 0 \\
-     \wedge & b^{|t|} \neq \bytes_t(c) \\
+     (\iff & \X{ea} + N/8 \leq n \\
+     \wedge & \X{ea} \mod N/8 = 0 \\
+     \wedge & b^{N} \neq \bytes_t(c) \\
      \end{array}
    \\[1ex]
    \begin{array}{lcl@{\qquad}l}
-   F; (\I64.\CONST~k)~(t.\CONST~c)~(\I32.\CONST~i)~t.\ATOMICWAIT
+   F; (\I64.\CONST~k)~(\iN.\CONST~c)~(\I32.\CONST~i)~\MEMORYATOMICWAIT{N}
      &\stepto^{(\ARD~a.\LLEN~n)}&
      F; \TRAP
    \end{array}
    \\ \qquad
      \begin{array}[t]{@{}r@{~}l@{}}
-     (\iff i + |t|/8 > n \vee i \mod |t|/8 \neq 0) \\
+     (\iff i + N/8 > n \vee i \mod N/8 \neq 0) \\
      \end{array}
    \\[2ex]
    \begin{array}[t]{@{}r@{~}l@{}}
@@ -1017,8 +1017,8 @@ See :ref:`above <exec-atomic-store>`.
 
 .. _exec-notify:
 
-:math:`\ATOMICNOTIFY`
-.....................
+:math:`\MEMORYATOMICNOTIFY`
+...........................
 
 .. todo:: update to new rules
 .. todo:: add text; operand order? is the trap case correct (issue #105)?

document/core/syntax/instructions.rst

@@ -287,8 +287,8 @@ Instructions in this group are concerned with accessing :ref:`linear memory <syn
      \ATOMICXCHG \\
    \production{instruction} & \instr &::=&
      \dots ~|~ \\&&&
-     \ATOMICNOTIFY~\memarg ~|~ \\&&&
-     \K{i}\X{nn}\K{.}\ATOMICWAIT~\memarg ~|~ \\&&&
+     \MEMORYATOMICNOTIFY~\memarg ~|~ \\&&&
+     \MEMORYATOMICWAIT\X{nn}~\memarg ~|~ \\&&&
      \K{i}\X{nn}\K{.}\ATOMICLOAD~\memarg ~|~ \\&&&
      \K{i}\X{nn}\K{.}\ATOMICSTORE~\memarg ~|~ \\&&&
      \K{i}\X{nn}\K{.}\ATOMICLOAD\K{8\_u}~\memarg ~|~
@@ -324,13 +324,13 @@ this action conditionally, if the read value is equal to a provided comparison
 argument. All other :ref:`atomicops <syntax-atomicop>` have behavior of the
 :ref:`ibinop <syntax-ibinop>` of the same name.
 
-The |ATOMICWAIT| and |ATOMICNOTIFY| instructions provide primitive
-synchronization between :ref:`threads <syntax-thread>`. The |ATOMICWAIT|
+The |MEMORYATOMICWAIT| and |MEMORYATOMICNOTIFY| instructions provide primitive
+synchronization between :ref:`threads <syntax-thread>`. The |MEMORYATOMICWAIT|
 instructions atomically load a value from the calculated effective address and
 compare it to an expected value. If they are equal, the thread is then
 suspended until a given timeout expires or another thread wakes it. The
-|ATOMICNOTIFY| instruction wakes threads that are waiting on a given address, up
-to a given maximum.
+|MEMORYATOMICNOTIFY| instruction wakes threads that are waiting on a given
+address, up to a given maximum.
 
 
 .. index:: ! control instruction, ! structured control, ! label, ! block, ! branch, ! unwinding, result type, label index, function index, type index, vector, trap, function, table, function type

document/core/text/instructions.rst

@@ -241,9 +241,9 @@ The offset immediate to atomic memory instructions is optional, and defaults to
 .. math::
    \begin{array}{llclll}
    \production{instruction} & \Tplaininstr_I &::=& \dots \phantom{thisshouldbeenoughnowitissee} && \phantom{thisshouldbeenough} \\ &&|&
-     \text{atomic.notify}~~m{:}\Tmemarg_4 &\Rightarrow& \ATOMICNOTIFY~m \\ &&|&
-     \text{i32.atomic.wait}~~m{:}\Tmemarg_4 &\Rightarrow& \I32.\ATOMICWAIT~m \\ &&|&
-     \text{i64.atomic.wait}~~m{:}\Tmemarg_8 &\Rightarrow& \I64.\ATOMICWAIT~m \\
+     \text{memory.atomic.notify}~~m{:}\Tmemarg_4 &\Rightarrow& \MEMORYATOMICNOTIFY~m \\ &&|&
+     \text{memory.atomic.wait32}~~m{:}\Tmemarg_4 &\Rightarrow& \MEMORYATOMICWAIT{32}~m \\ &&|&
+     \text{memory.atomic.wait64}~~m{:}\Tmemarg_8 &\Rightarrow& \MEMORYATOMICWAIT{64}~m \\
    \end{array}
 
 .. math::

document/core/util/macros.def

@@ -379,8 +379,8 @@
 .. |REINTERPRET| mathdef:: \xref{syntax/instructions}{syntax-instr-numeric}{\K{reinterpret}}
 
 .. |ATOMIC| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{atomic}}
-.. |ATOMICWAIT| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{atomic.wait}}
-.. |ATOMICNOTIFY| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{atomic.notify}}
+.. |MEMORYATOMICWAIT| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{memory.atomic.wait}}
+.. |MEMORYATOMICNOTIFY| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{memory.atomic.notify}}
 .. |ATOMICADD| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{add}}
 .. |ATOMICSUB| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{sub}}
 .. |ATOMICAND| mathdef:: \xref{syntax/instructions}{syntax-instr-atomic-memory}{\K{and}}

document/core/valid/instructions.rst

@@ -433,8 +433,8 @@ Atomic Memory Instructions
 
 .. _valid-atomic-notify:
 
-:math:`\ATOMICNOTIFY~\memarg`
-.............................
+:math:`\MEMORYATOMICNOTIFY~\memarg`
+...................................
 
 * The memory :math:`C.\CMEMS[0]` must be defined in the context.
 
@@ -450,29 +450,29 @@ Atomic Memory Instructions
      \qquad
      2^{\memarg.\ALIGN} = 4
    }{
-     C \vdash \ATOMICNOTIFY~\memarg : [\I32~\I64] \to [\I64]
+     C \vdash \MEMORYATOMICNOTIFY~\memarg : [\I32~\I64] \to [\I64]
    }
 
 .. _valid-atomic-wait:
 
-:math:`t\K{.}\ATOMICWAIT~\memarg`
-.................................
+:math:`\MEMORYATOMICWAIT{N}~\memarg`
+....................................
 
 * The memory :math:`C.\CMEMS[0]` must be defined in the context.
 
 * Let :math:`\limits~\share` be the :ref:`memory type <syntax-memtype>` :math:`C.\CMEMS[0]`.
 
-* The alignment :math:`2^{\memarg.\ALIGN}` must be equal to the :ref:`width <syntax-valtype>` of :math:`t` divided by :math:`8`.
+* The alignment :math:`2^{\memarg.\ALIGN}` must be equal to :math:`N` divided by :math:`8`.
 
-* Then the instruction is valid with type :math:`[\I32~t~\I64] \to [\I32]`.
+* Then the instruction is valid with type :math:`[\I32~\K{i}{N}~\I64] \to [\I32]`.
 
 .. math::
    \frac{
      C.\CMEMS[0] = \memtype
      \qquad
-     2^{\memarg.\ALIGN} = |t|/8
+     2^{\memarg.\ALIGN} = N/8
    }{
-     C \vdash t\K{.}\ATOMICWAIT~\memarg : [\I32~t~\I64] \to [\I32]
+     C \vdash \MEMORYATOMICWAIT{N}~\memarg : [\I32~\K{i}{N}~\I64] \to [\I32]
    }
 
 .. _valid-atomic-load:

interpreter/binary/decode.ml

@@ -209,9 +209,9 @@ let memop s =
 let atomic_instr s =
   let pos = pos s in
   match op s with
-  | 0x00 -> let a, o = memop s in atomic_notify a o
-  | 0x01 -> let a, o = memop s in i32_atomic_wait a o
-  | 0x02 -> let a, o = memop s in i64_atomic_wait a o
+  | 0x00 -> let a, o = memop s in memory_atomic_notify a o
+  | 0x01 -> let a, o = memop s in memory_atomic_wait32 a o
+  | 0x02 -> let a, o = memop s in memory_atomic_wait64 a o
 
   | 0x10 -> let a, o = memop s in i32_atomic_load a o
   | 0x11 -> let a, o = memop s in i64_atomic_load a o

interpreter/binary/encode.ml

@@ -207,17 +207,18 @@ let encode m =
       | Store ({ty = I64Type; sz = Some Pack32; _} as mo) -> op 0x3e; memop mo
       | Store {ty = F32Type | F64Type; sz = Some _; _} -> assert false
 
-      | AtomicNotify ({ty = I32Type; sz = None; _} as mo) ->
+      | MemoryAtomicNotify ({ty = I32Type; sz = None; _} as mo) ->
         op 0xfe; op 0x00; memop mo
-      | AtomicNotify {ty = I32Type; sz = Some _; _} -> assert false
-      | AtomicNotify {ty = I64Type | F32Type | F64Type; _} -> assert false
+      | MemoryAtomicNotify {ty = I32Type; sz = Some _; _} -> assert false
+      | MemoryAtomicNotify {ty = I64Type | F32Type | F64Type; _} -> assert false
 
-      | AtomicWait ({ty = I32Type; sz = None; _} as mo) ->
+      | MemoryAtomicWait ({ty = I32Type; sz = None; _} as mo) ->
         op 0xfe; op 0x01; memop mo
-      | AtomicWait ({ty = I64Type; sz = None; _} as mo) ->
+      | MemoryAtomicWait ({ty = I64Type; sz = None; _} as mo) ->
         op 0xfe; op 0x02; memop mo
-      | AtomicWait {ty = I32Type | I64Type; sz = Some _; _} -> assert false
-      | AtomicWait {ty = F32Type | F64Type; _} -> assert false
+      | MemoryAtomicWait {ty = I32Type | I64Type; sz = Some _; _} ->
+          assert false
+      | MemoryAtomicWait {ty = F32Type | F64Type; _} -> assert false
 
       | AtomicLoad ({ty = I32Type; sz = None; _} as mo) ->
         op 0xfe; op 0x10; memop mo

interpreter/exec/eval.ml

@@ -276,8 +276,7 @@ let rec step (c : config) : config =
           v1 :: vs', []
         with exn -> vs', [Trapping (memory_error e.at exn) @@ e.at]);
 
-      | AtomicWait {offset; ty; sz; _}, I64 timeout :: ve :: I32 i :: vs' ->
-        (* TODO: Trap if memory is not shared *)
+      | MemoryAtomicWait {offset; ty; sz; _}, I64 timeout :: ve :: I32 i :: vs' ->
         let mem = memory frame.inst (0l @@ e.at) in
         let addr = I64_convert.extend_i32_u i in
         (try
@@ -290,7 +289,7 @@ let rec step (c : config) : config =
             I32 1l :: vs', []  (* Not equal *)
         with exn -> vs', [Trapping (memory_error e.at exn) @@ e.at])
 
-      | AtomicNotify x, I32 count :: I32 i :: vs' ->
+      | MemoryAtomicNotify x, I32 count :: I32 i :: vs' ->
           if count = 0l then
             I32 0l :: vs', []  (* Trivial case waking 0 waiters *)
           else