From ec0228f1bd89f725ce23a27c494659af4ad183fa Mon Sep 17 00:00:00 2001 From: sneha-voona Date: Tue, 8 Sep 2026 14:47:48 +0530 Subject: [PATCH] acp_7_x: clear DMA IO stutter and PWA defaults to fix I2S loopback noise ACP DMA linked-list, IO stutter, and PWA control registers retain power-on defaults that can affect I2S DMA transfers: - ACP_DMA_CH_LINKED_LIST_EN: DMAChIOStutEn (bits 24:15) defaults to all 1s - ACP_DMA_IO_STUT_TIMER_LIMIT: IO stutter timer defaults are non-zero - ACP_DMA_CH_PWA_CTRL: PWA DMA control defaults are enabled Clear these registers during platform init, before DMA channel setup, to disable DMA IO stutter and PWA features that cause I2S loopback noise. Signed-off-by: sneha-voona --- .../amd/acp_7_x/include/platform/platform_misc.h | 3 +++ src/platform/amd/acp_7_x/platform.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/platform/amd/acp_7_x/include/platform/platform_misc.h b/src/platform/amd/acp_7_x/include/platform/platform_misc.h index 949f3622374f..7898c6bc24f0 100644 --- a/src/platform/amd/acp_7_x/include/platform/platform_misc.h +++ b/src/platform/amd/acp_7_x/include/platform/platform_misc.h @@ -24,6 +24,9 @@ #define ACP_SRBM_CLIENT_RDDATA 0x1241BF4 #define ACP_SRBM_CYCLE_STS 0x1241BF8 #define ACP_SRBM_CLIENT_CONFIG 0x1241BFC +#define ACP_DMA_CH_LINKED_LIST_EN 0x124012C +#define ACP_DMA_IO_STUT_TIMER_LIMIT 0x1240130 +#define ACP_DMA_CH_PWA_CTRL 0x1240138 /* Registers from SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6 block ACP_7X */ #define ACP_7X_SYSTEMPLL2P0_N3_BUS_CSR_SNAP_6_REFCLK_BRDS 0x6D204 diff --git a/src/platform/amd/acp_7_x/platform.c b/src/platform/amd/acp_7_x/platform.c index f6778dd0bf98..fbe5e10a487b 100644 --- a/src/platform/amd/acp_7_x/platform.c +++ b/src/platform/amd/acp_7_x/platform.c @@ -150,6 +150,16 @@ int platform_init(struct sof *sof) /*CONFIG_SYSTICK_PERIOD hardcoded as 200000*/ sa_init(sof, 200000); clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ); + + /* + * Clear DMA linked-list IO stutter and PWA defaults before + * channel setup. ACP_DMA_CH_LINKED_LIST_EN DMAChIOStutEn + * (bits 24:15) defaults to all 1s. + */ + io_reg_write(PU_REGISTER_BASE + ACP_DMA_CH_LINKED_LIST_EN, 0); + io_reg_write(PU_REGISTER_BASE + ACP_DMA_IO_STUT_TIMER_LIMIT, 0); + io_reg_write(PU_REGISTER_BASE + ACP_DMA_CH_PWA_CTRL, 0); + /* init DMA */ ret = dmac_init(sof); if (ret < 0) {