Conversation
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I know this PR is quite dated but I would also like to have this feature. Willing to rebase. |
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Noted! Can you tell us a bit more how you'd use this feature? When the PR was first discussed, we weren't sure of the intended usage. In the meantime, you can always use inline assembly: |
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I am formally verifying libsecp256k1 and SHRINCS with CompCert and VST. SHRINCS uses Builtin support would avoid architecture-specific inline assembly and let the CompCert build trap too. For precision, secp256k1 currently uses abort. |
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Thank you for the context and the extra information. For reference, I looked at how GCC and Clang implement
Things are pretty clear for AArch64, Power and x86, but I'm intrigued they choose different instructions for ARMv7 and RISC-V. |
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For RISC-V, there is not really a standardised encoding for a well-defined unimplemented instruction. The RISC-V Instruction Set Manual, Volume I (Unprivileged Architecture) has the following note for instruction EBREAK:
The RISC-V ASM manual specifies some instruction aliases. One of them is UNIMP:
Given that UNIMP needs ISA extension Zicsr, I think EBREAK is the better choice for |
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The instruction encoding for UDF allows to specify a 16-bit immediate constant that is ignored by hardware. The variants used by GCC and Clang for ARMv7 just differ in that immediate value and hence, should be functionally equivalent. |
This PR adds support for
__builtin_trapon x86, mapped to theud2instruction. I copied how this was done for PowerPC.Should I instead add a case for the
Pbuiltinpseudo-instruction?