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Test RISC-V Backend
Test RISC-V Backend #99: Scheduled
Queued main
Test RISC-V Backend
Test RISC-V Backend #98: Scheduled
1d 0h 0m 4s main
Test RISC-V Backend
Test RISC-V Backend #97: Scheduled
23h 17m 30s main
Sym ite prim op (#20681)
Test RISC-V Backend #96: Commit 8965e51 pushed by chenweng-quic
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #94: Scheduled
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #92: Scheduled
1d 0h 0m 2s main
Test RISC-V Backend
Test RISC-V Backend #91: Scheduled
1d 0h 0m 3s main
NXP backend: Enable Neg with new Neutron flow (#20451)
Test RISC-V Backend #90: Commit 2af5638 pushed by qti-horodnic
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #89: Scheduled
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #88: Scheduled
1d 0h 0m 2s main
Test RISC-V Backend
Test RISC-V Backend #87: Scheduled
1d 0h 0m 4s main
Test RISC-V Backend
Test RISC-V Backend #86: Scheduled
23h 16m 27s main
Arm backend: Bump vela to 5.1.0 (#20181)
Test RISC-V Backend #85: Commit 23e9bec pushed by shewu-quic
1d 0h 0m 2s main
Test RISC-V Backend
Test RISC-V Backend #84: Scheduled
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #82: Scheduled
1d 0h 0m 2s main
Test RISC-V Backend
Test RISC-V Backend #80: Scheduled
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #78: Scheduled
1d 0h 0m 3s main
Test RISC-V Backend
Test RISC-V Backend #76: Scheduled
1d 0h 0m 2s main
Test RISC-V Backend
Test RISC-V Backend #75: Scheduled
1d 0h 0m 2s main