feat: add bitpacked v2 serialization

[mhk197]

Serialize varying widths under fastlanes.bitpacked_v2 with width and offset children and bounded metadata. Uniform arrays retain the original v1 wire contract. Add recursive round trips, compressed-layout execution, and cross-format rejection tests; CUDA support remains uniform-only. Extract the shared wire-format helpers here, preserving the v1 validation order introduced earlier in the stack.

Part 6/9 of the bitpacked-v2 stack (735 added + removed lines). Merge in order; each draft targets the preceding branch, starting from develop.

1 → 2 → 3 → 4 → 5 → 6 → 7 → 8 → 9

Validation: After restacking, the complete stack passes 435 FastLanes/BtrBlocks tests (1 skipped), 4 FastLanes doctests, focused Clippy with --all-targets --all-features -- -D warnings, and cargo +nightly fmt --all -- --check. Focused serde/layout tests also pass on PRs 3, 5, and 6 (10, 17, and 28 tests respectively); git diff --check passes throughout the stack.

[codspeed]

Merging this PR will degrade performance by 52.37%

⚠️ Unknown Walltime execution environment detected

Using the Walltime instrument on standard Hosted Runners will lead to inconsistent data.

For the most accurate results, we recommend using CodSpeed Macro Runners: bare-metal machines fine-tuned for performance measurement consistency.

⚠️ Different runtime environments detected

Some benchmarks with significant performance changes were compared across different runtime environments,
which may affect the accuracy of the results.

Open the report in CodSpeed to investigate

⚡ 76 improved benchmarks
❌ 218 regressed benchmarks
✅ 1890 untouched benchmarks
🆕 24 new benchmarks
⏩ 287 skipped benchmarks¹

Warning

Please fix the performance issues or acknowledge them on CodSpeed.

Performance Changes

	Mode	Benchmark	BASE	HEAD	Efficiency
❌	Simulation	allocate_drop_vortex_minimal_alignment[1024]	2.9 µs	95.3 µs	-96.99%
❌	Simulation	from_vec_drop_vortex[1024]	3.1 µs	102.2 µs	-96.94%
❌	Simulation	from_vec_drop_vortex[256]	3.1 µs	93.6 µs	-96.72%
❌	Simulation	from_vec_drop_arrow[1024]	2.9 µs	86.6 µs	-96.69%
❌	Simulation	from_vec_drop_arrow[256]	2.8 µs	83.8 µs	-96.64%
❌	Simulation	from_vec_drop_bytes[1024]	2.2 µs	60.2 µs	-96.37%
❌	Simulation	from_vec_drop_vortex[64]	3 µs	80.9 µs	-96.27%
❌	Simulation	allocate_freeze_drop_bytes[256]	3.2 µs	85.2 µs	-96.22%
❌	Simulation	allocate_freeze_drop_vortex_minimal_alignment[1024]	5.3 µs	137.4 µs	-96.16%
❌	Simulation	allocate_freeze_drop_vortex_custom[64]	4.2 µs	108.2 µs	-96.12%
❌	Simulation	allocate_freeze_drop_vortex_minimal_alignment[64]	3.3 µs	83.5 µs	-96.02%
❌	Simulation	from_vec_drop_bytes[256]	2.2 µs	54.7 µs	-96.01%
❌	Simulation	from_vec_drop_arrow[64]	2.8 µs	70.1 µs	-95.99%
❌	Simulation	allocate_freeze_drop_vortex[64]	3.4 µs	84.7 µs	-95.94%
❌	Simulation	allocate_freeze_drop_vortex[256]	3.5 µs	85.6 µs	-95.92%
❌	Simulation	allocate_freeze_drop_bytes[1024]	3.3 µs	77.9 µs	-95.79%
❌	Simulation	allocate_freeze_drop_vortex_minimal_alignment[65536]	6 µs	140 µs	-95.75%
❌	Simulation	allocate_drop_vortex[256]	2.9 µs	67.5 µs	-95.74%
❌	Simulation	allocate_freeze_drop_vortex_minimal_alignment[16384]	6 µs	139.6 µs	-95.74%
❌	Simulation	allocate_drop_vortex[64]	2.9 µs	66.7 µs	-95.69%
...	...	...	...	...	...

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Tip

Investigate this regression by commenting @codspeedbot fix this regression on this PR, or directly use the CodSpeed MCP with your agent.

---

_{Comparing mk/bitpacked-stack-06-v2-wire (377f70c) with mk/bitpacked-stack-05-explicit-packing (120d3bd)²}

Footnotes

1. 287 benchmarks were skipped, so the baseline results were used instead. If they were deleted from the codebase, click here and archive them to remove them from the performance reports. ↩

2. No successful run was found on mk/bitpacked-stack-05-explicit-packing (b055b6b) during the generation of this report, so 9f467b2 was used instead as the comparison base. There might be some changes unrelated to this pull request in this report. ↩